1. Field of the Invention
The present invention relates generally to electronic packaging of semiconductor integrated circuits. More specifically, the present invention relates to electronic packaging of image-sensing semiconductor devices.
2. Related Art
Image sensors (or image-sensing semiconductor devices) find wide use in various digital photography applications. They are used in digital cameras and camcorder, for which the market has grown sharply since about 1999 when manufacturers began incorporating in cellular phone devices.
As shown in FIG. 1, an image sensor die 2 includes an image-sensing area 4 (the so-called “pixel area”) at its center, and electrical terminals 6 (the so-called “bonding pads”) about its peripheral areas for electrical input and output. Typically, the image-sensing area 4 includes a plurality of photo-diodes disposed underneath which serve to transduce light to electrical signals. Red, green, and blue color filters are disposed over the photo-diodes for differentiating the color of the incoming light. Micro-lenses are in turn disposed over the color filters for improving light intensity passing on to the photo-diodes. In the image sensor die configuration schematically illustrated in FIG. 1, only the image sensing area 4 and terminals 6 are shown for brevity and clarity.
Generally, semiconductor devices have been packaged in the so-called “plastic package,” having epoxy molding compound fully enclosing the device for protection. In the case of image sensors, however, light must pass to the image-sensing area. Therefore, such plastic package is generally not suitable as electronic packaging for image sensors.
Ceramic packages having glass lid tops have been used for image sensor packaging. On such package is illustrated in schematic cross-section in FIG. 2. As shown in the figure, this ceramic package 10 includes a multi-layered ceramic substrate 14 and an image sensor chip 12 attached at a central portion of the substrate using epoxy or the like. Gold wires electrically connect the image sensor chip and substrate. A glass lid 16 is attached at a top of the package to allow the passage of light into the image sensor chip's image-sensing area.
This ceramic package has superior robustness. However, it is ordinarily very expensive. Moreover, the package in most cases is not small enough for hand-held applications like cellular phones. Because of these factors, use of such ceramic package is seen primarily in applications where high reliability is of greater concern than compact size or low price, such as digital camera or camcorder applications. Use of the package is not often seen in applications like camera phones, where low price and compact size are more important concerns than reliability.
Although not separately shown, a plastic package is also known in the art which incorporates typical lead frame and molding compound features, but includes a glass lid top to serve as an image sensor package, employing a plastic leadless chip carrier (PLCC) configuration. Such a package structure is well known to persons versed in image sensor packaging art. A notable advantage is that it tends to be less in cost than the ceramic package. However, it is not as robust as the ceramic package, and is no more compact than a comparable ceramic package. For these reasons, such plastic package structure has been used primarily in certain PC camera applications where low price is the most important of requirements, over such others as reliability or size.
Another packaging option proposed in the art for an image sensor is one having a laminate substrate instead of ceramic, but with much the same configuration as a ceramic package. This option may prove a bit cheaper in cost, but also fails to provide the degree of compactness normally required for hand-held applications. A figure schematic illustrating this package is omitted for brevity and clarity, as such package structure is well known to persons versed in image sensor packaging art.
The packages mentioned above fail to provide sufficient compactness for hand-held applications such as cellular phone. Chip scale (or size) packaging (CSP) technology for image sensors having low price and small size has drawn much interest in the art for hand-held applications, given the enormous recent growth of the market.
CSP technology suitable for image sensor was proposed by Shellcase Inc. Detailed techniques relating to this technology are disclosed in U.S. Pat. Nos. 5,716,759, 6,040,235, and 6,117,707, for example. FIG. 3 illustrates a schematic cross-section of a package formed according to this technology. For better understanding of the advantages and disadvantages of the package, it is helpful to explain the method for forming the structure. First, an image sensor wafer is provided with bonding pads extended to its dicing areas which have narrow widths between neighboring dice. The dicing width must be sufficiently wider than the approximate 100 micro-meters normally used in the semiconductor industry. This special requirement limits the package's application in practice.
To form a package 20 shown in FIG. 3 according to this technique, a front side of an image sensor wafer 22 is attached to a glass wafer 24 using epoxy 21 or the like. Then, a backside of the image sensor wafer is thinned by grinding. Generally, the wafer thickness before thinning is about 725 micro-meters, and about 100 micro-meters after it is thinned. A detailed explanation as to the need for such thinning is omitted herein for brevity and clarity.
Afterwards, another glass wafer is attached to the backside of the image sensor wafer by using epoxy or the like. Then the wafer is partially diced up to sufficient depth that the terminals extending to the dicing line are exposed. Special dicing blades having a certain tip angle is used for this operation to form a ditch-like structure where terminals are exposed at inner surfaces of the ditch. Interconnection metal lines are thereafter formed over the surface by metal layer depositing and patterning. Additional description of further processing steps necessary to complete this package are omitted for brevity and clarity.
A most important advantage of this technique is that the resulting package size is about the same as the image sensor die size. However, there are several critical drawbacks in this technique. The most critical drawback is that the structure is too complicated, and the process technique is too difficult. Detailed explanations are again omitted for brevity and clarity, but such drawbacks are well known to persons versed in the wafer level packaging art. Because of these drawbacks, required manufacturing costs tend to be prohibitively high, and sufficiently high yields tend to be difficult to achieve, which in turn also increases overall manufacturing costs.
Other drawbacks are found with this technique. One of them is that the image sensor wafer has to meet certain special requirements, like terminals having to be extended to the dicing area and the pertinent width having to be substantially larger than normal as a result. This tends to decrease the total number of dice realizable on a given wafer, given the need for wider dicing lines. In practice, an image sensor maker employing this technique is forced to produce multiple wafer types, one adapted for this packaging technique, and another of more conventional configuration for other general packaging techniques. This results in additional costs.
Yet another disadvantage to this technique is that all dice on wafers are subjected to all the manufacturing processes in this technique. The manufacturing cost depends quite heavily on the yield of each image sensor wafer in this kind of situation. In the example of one device having an 80% image sensor wafer yield and another having a 40% yield, the unit package manufacturing cost (or price) in the latter case would be double that in the former case. The reality presently is that even matured image sensor devices in production have typically about a 70% yield; and, image sensor makers typically start mass production at about a 30% yield. With high resolution image sensors, the wafer yield could be even lower than 30% in production, since wafer yield is inversely related to resolution. Given such circumstances, it is not easy to adopt this technique for packaging an image sensor wafer. The technique is not used much for these reasons, even though it provides superior compact package size advantages.
A major source of failure in image sensor packaging is particles adhered to image sensing area surfaces. This causes repeatable spotting in the resultant digital images. Even though particles may not actually stick to image sensing area surfaces, but instead moves inside of the package, the persistent if not repeatable spotting which results in the resultant digital images is equally unacceptable. Contamination of the image sensing area otherwise may cause the same kind of failure. Therefore, it is critical in image sensor packaging to minimize or prevent any particle entry or other contamination, especially at the image sensing area. That is why higher cleanness is particularly essential in image sensor packaging than in other types of packaging.
Image sensor packages typically include a sealing structure for preventing particles from reaching and entering the image sensing area. For instance, a ceramic package for image sensor includes a glass lid on top of the package, with a cavity formed inside, such that particles are prevented from getting inside once the glass lid is placed and attached onto the package.
Humidity uptake inside the image sensing area is also known to degrade a color filter and micro-lens disposed thereon. This does not appear to be a significant issue with many digital cameras, but in the case of high-end, professional-grade digital cameras, for instance, hermetic or other protective measures have been sought to prevent or minimize the humidity uptake.
A package having a hermetic metal sealing structure was proposed by IMEC, VZW. Detailed techniques relating to such structure are disclosed in U.S. Pat. No. 6,566,745. FIGS. 4a and 4b illustrate the package structure. As shown in the figures, this package 30 includes flip chip solder joints 33 for electrical interconnection between an image sensor die 32 and a glass substrate 31. Also, this package includes solder balls 34 which serve as package's external terminals, as well as metal lines 37 formed on the glass substrate for connecting the solder balls and flip chip solder joints. This package further includes a solder sealing ring 35 having a closed loop configuration. In addition, the package includes epoxy sealing 36 disposed about the solder sealing ring. Other components are not shown, in the interests of brevity and clarity.
The metal sealing structure provides a hermetic seal for preventing particle or humidity uptake, while epoxy sealing structure provides a non-hermetic seal inasmuch as that it permits some amount of humidity to get inside by diffusion.
This IMEC, VZW package strives for the most ideal sealing structure for image sensors, but substantial difficulties must be overcome in actually forming the structure. First of all, this package requires a vacuum solder reflow process instead of a conventional convection reflow process or the like. Normally, a flip chip die collapses when solder bumps melt and wet to pads of the substrate during a solder reflow process. That is, the height of a flip chip solder joint formed by a solder reflow process is substantially less than that of the original flip chip solder bump. Solder bumps 50 micro-meters in height, for example, typically form solder joints approximately just 30 micro-meters high. The amount of collapse mainly depends on the pad size on substrate. For instance, if the pad size were infinite, the collapse would be 100%, and the solder joint height would conversely be zero. On the other hand, if the pad size were to approach zero, the amount of collapse would also approach zero, and the solder joint height will remain the same as the solder bump height. While further explanation is omitted, this is well known to persons versed in the soldering art.
The IMEC, VZW package includes a solder sealing ring structure having a closed loop configuration. As the solder material melts and wets to pads on the substrate, the solder sealing ring necessarily tends toward some collapse. If not done within a vacuum environment, the air entrapped within the cavity surrounded by the ring would hinder this collapse of not only the solder sealing ring but also the flip chip bumps. This would increase failure rate in forming solder joints, which in turn increases yield loss. Therefore, vacuum solder reflow or the like is essential for properly forming this structure.
A fluxless soldering technique is also essential for properly forming this structure. Normally, flux is applied onto joining areas of objects to be adjoined by soldering. Flux removes oxide from surface of joining objects and also prevents oxidation during a solder reflow process. It includes a solvent that evaporates early in the reflow process, at about 60°–100° C. depending on the given flux material characteristics. This is called “out-gassing.” In the IMEC, VZW package structure, there is no path by which the solvent can evacuate since a closed cavity is maintained. Residual solvent in the cavity would prove detrimental to long term reliability, and may also cause contamination of the image sensing area. Therefore, the IMEC, VZW package structure necessitates a fluxless soldering technique to properly form its sealing structure.
Conventional solder reflow techniques, like the so-called surface mounting technique (SMT), is quite inexpensive and reliable. This technique includes flux application on joining areas, and permits the transport of objects to be adjoined through a belt (conveyor) oven. A vacuum reflow technique, on the other hand, is not common in industry even though it has been tried for research purposes. Hence, there is no vacuum reflow equipment for mass production commercially available presently on the market.
A vacuum reflow oven would not necessarily be difficult to build. A possible configuration of the equipment may include a vacuum chamber and a robot system to handle wafer transport in and out. Also the equipment may include infrared (IR) lamps to heat the wafer through a glass window of the vacuum chamber. The temperature control would not be as simple as for a conventional belt oven. The equipment price, however, would be considerably higher than that for a conventional belt oven. The throughput would be much lower considering that processing of the next wafer must await complete processing of the wafer then in the vacuum chamber, whereas wafers may be continually transported for processing through a conventional belt oven.
The required fluxless soldering for forming this package structure would add further costs and complexity. Detailed explanation in that regard is omitted, however, for brevity and clarity.